1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a semiconductor memory device for storing data in memory cells.
2. Description of the Related Art
In general, semiconductor memory devices are divided into volatile memory devices, such as Dynamic Random Access Memory (DRAM) devices and Static Random Access Memory (SRAM) devices, and non-volatile memory devices, such as Programmable Read Only Memory (PROM) devices, Erasable PROM (EPROM) devices, and flash memory devices. Non-volatile memory devices and volatile memory devices are distinguished based on whether the data stored in a memory cell is retained or not after a certain time passes from the storage of the data. In other words, the non-volatile memory devices retain the data stored in a memory cell, whereas the volatile memory devices lose the data stored in a memory cell as time passes. The volatile memory devices perform a refresh operation essentially to maintain data. On the other hand, the non-volatile memory devices may not perform a refresh operation. Since such a feature of the non-volatile memory devices is appropriate for low power consumption and high integration, the non-volatile memory devices are widely used as storage media of portable devices.
Meanwhile, as the fabrication technology of semiconductor memory devices has advanced, the integration degree of semiconductor memory devices has been increased greatly. The increase in the integration degree has decreased the chip size of semiconductor memory devices and eventually, the space between the memory cells disposed therein has become narrow. The space has become so narrow that the data stored in one memory cell may affect the data of the adjacent memory cells, and a technology of randomly storing data to minimize the interference between the adjacent memory cells is being developed. The core part of the data randomizing technology includes a linear feedback shift register that generates a random value and an initial value generation circuit that generates a random initial value for address mapping.
The linear feedback shift register and the initial value generation circuit may occupy a relatively wide area, and the control of the linear feedback shift register and the initial value generation circuit is quite complicated. As described above, the linear feedback shift register and the initial value generation circuit are essential constituent elements in the conditions that semiconductor memory devices are being integrated higher and higher. However, since the linear feedback shift register and the initial value generation circuit occupy a large area, their use in a semiconductor memory device is difficult to implement.